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/*
* TU Eindhoven
* Eindhoven, The Netherlands
*
* Name : bram8k.h
*
* Author : A.S.Slusarczyk@tue.nl
*
* Date :
*
* Function : RAM based on VirtexII 16kb BlockRAMs
* For byte-level and debugging access, four 8-bit-wide blocks are necessary, so
* the size of the memory is 4x16kb = 64kb = 8kB
* Actually, the parity bits add another 1kB, but it's unused
*
*/
#ifndef BRAM8K_H_INCLUDED
#define BRAM8K_H_INCLUDED
#include "mips.h"
#include "xlxram.h"
// BlockRAM wrapper
SC_MODULE(BRAM8KCONV) {
sc_in < sc_bv > addr;
sc_out< sc_bv > dout;
sc_in< sc_bv > din;
sc_in< sc_bv > w;
sc_in< sc_bv > r;
sc_in< bool > clk;
sc_in< sc_bv<1> > en;
sc_out< bool > memwait;
sc_in > DO0, DO1, DO2, DO3;
sc_in > DOP0, DOP1, DOP2, DOP3;
sc_out > ADDR0, ADDR1, ADDR2, ADDR3;
sc_out > DI0, DI1, DI2, DI3;
sc_out > DIP0, DIP1, DIP2, DIP3;
sc_out EN0, EN1, EN2, EN3;
sc_out CLK0, CLK1, CLK2, CLK3;
sc_out WE0, WE1, WE2, WE3;
sc_out SSR0, SSR1, SSR2, SSR3;
// registered input signals
sc_signal< sc_bv > w_reg;
sc_signal< sc_bv > r_reg;
sc_signal< sc_bv<2> > byte_reg;
void in();
void out();
void reg();
SC_CTOR(BRAM8KCONV) {
SC_METHOD(in);
sensitive << addr << din << w << r << en << clk;
SC_METHOD(out);
sensitive << DO0 << DO1 << DO2 << DO3 << DOP0 << DOP1 << DOP2 << DOP3
<< w_reg << r_reg << byte_reg;
SC_METHOD(reg);
sensitive_pos << clk;
};
};
// Converter for the debugging access
// Debug does not require byte-level access, so converter can be much simpler
SC_MODULE(DBGBRAM8KCONV) {
sc_out > DO;
sc_in > ADDR;
sc_in > DI;
sc_in EN;
sc_in CLK;
sc_in WE;
sc_in RST;
sc_in > DO0, DO1, DO2, DO3;
sc_in > DOP0, DOP1, DOP2, DOP3;
sc_out > ADDR0, ADDR1, ADDR2, ADDR3;
sc_out > DI0, DI1, DI2, DI3;
sc_out > DIP0, DIP1, DIP2, DIP3;
sc_out EN0, EN1, EN2, EN3;
sc_out CLK0, CLK1, CLK2, CLK3;
sc_out WE0, WE1, WE2, WE3;
sc_out SSR0, SSR1, SSR2, SSR3;
void in();
void out();
SC_CTOR(DBGBRAM8KCONV) {
SC_METHOD(in);
sensitive << ADDR << DI << EN << WE << RST << CLK;
SC_METHOD(out);
sensitive << DO0 << DO1 << DO2 << DO3 << DOP0 << DOP1 << DOP2 << DOP3;
};
};
// the RAM class is just an RTL module connecting BlockRAM with its wrapper(s)
SC_MODULE(BRAM8K) {
sc_in < sc_bv > addr;
sc_out< sc_bv > dout;
sc_in< sc_bv > din;
sc_in< sc_bv > w;
sc_in< sc_bv > r;
sc_in< bool > clk;
sc_in< sc_bv<1> > en;
sc_out< bool > memwait;
RAMB16_S9_S9 *bram0;
RAMB16_S9_S9 *bram1, *bram2, *bram3;
BRAM8KCONV *conv;
sc_signal > DO0, DO1, DO2, DO3;
sc_signal > DOP0, DOP1, DOP2, DOP3;
sc_signal > ADDR0, ADDR1, ADDR2, ADDR3;
sc_signal > DI0, DI1, DI2, DI3;
sc_signal > DIP0, DIP1, DIP2, DIP3;
sc_signal EN0, EN1, EN2, EN3;
sc_signal CLK0, CLK1, CLK2, CLK3;
sc_signal WE0, WE1, WE2, WE3;
sc_signal SSR0, SSR1, SSR2, SSR3;
DBGBRAM8KCONV *dbgconv;
// independent access to the second set of ports for debugging
sc_out > dbgDO;
sc_in > dbgADDR;
sc_in > dbgDI;
sc_in dbgEN;
sc_in dbgCLK;
sc_in dbgWE;
sc_in dbgRST;
sc_signal > dDO0, dDO1, dDO2, dDO3;
sc_signal > dDOP0, dDOP1, dDOP2, dDOP3;
sc_signal > dADDR0, dADDR1, dADDR2, dADDR3;
sc_signal > dDI0, dDI1, dDI2, dDI3;
sc_signal > dDIP0, dDIP1, dDIP2, dDIP3;
sc_signal dEN0, dEN1, dEN2, dEN3;
sc_signal dCLK0, dCLK1, dCLK2, dCLK3;
sc_signal dWE0, dWE1, dWE2, dWE3;
sc_signal dSSR0, dSSR1, dSSR2, dSSR3;
#ifndef VERILOG
void mem_init(const char *filename, int size=RAMSIZE);
void mem_dump(const char *filename, int size=RAMSIZE);
#endif
SC_CTOR(BRAM8K) {
bram0 = new RAMB16_S9_S9("bram0");
bram1 = new RAMB16_S9_S9("bram1");
bram2 = new RAMB16_S9_S9("bram2");
bram3 = new RAMB16_S9_S9("bram3");
conv = new BRAM8KCONV("conv");
bram1->DOA(DO1); conv->DO1(DO1);
bram0->DOA(DO0); conv->DO0(DO0);
bram1->DOPA(DOP1); conv->DOP1(DOP1);
bram0->DOPA(DOP0); conv->DOP0(DOP0);
bram1->ADDRA(ADDR1); conv->ADDR1(ADDR1);
bram0->ADDRA(ADDR0); conv->ADDR0(ADDR0);
bram1->DIA(DI1); conv->DI1(DI1);
bram0->DIA(DI0); conv->DI0(DI0);
bram1->DIPA(DIP1); conv->DIP1(DIP1);
bram0->DIPA(DIP0); conv->DIP0(DIP0);
bram1->ENA(EN1); conv->EN1(EN1);
bram0->ENA(EN0); conv->EN0(EN0);
bram1->CLKA(CLK1); conv->CLK1(CLK1);
bram0->CLKA(CLK0); conv->CLK0(CLK0);
bram1->WEA(WE1); conv->WE1(WE1);
bram0->WEA(WE0); conv->WE0(WE0);
bram1->SSRA(SSR1); conv->SSR1(SSR1);
bram0->SSRA(SSR0); conv->SSR0(SSR0);
bram3->DOA(DO3); conv->DO3(DO3);
bram2->DOA(DO2); conv->DO2(DO2);
bram3->DOPA(DOP3); conv->DOP3(DOP3);
bram2->DOPA(DOP2); conv->DOP2(DOP2);
bram3->ADDRA(ADDR3); conv->ADDR3(ADDR3);
bram2->ADDRA(ADDR2); conv->ADDR2(ADDR2);
bram3->DIA(DI3); conv->DI3(DI3);
bram2->DIA(DI2); conv->DI2(DI2);
bram3->DIPA(DIP3); conv->DIP3(DIP3);
bram2->DIPA(DIP2); conv->DIP2(DIP2);
bram3->ENA(EN3); conv->EN3(EN3);
bram2->ENA(EN2); conv->EN2(EN2);
bram3->CLKA(CLK3); conv->CLK3(CLK3);
bram2->CLKA(CLK2); conv->CLK2(CLK2);
bram3->WEA(WE3); conv->WE3(WE3);
bram2->WEA(WE2); conv->WE2(WE2);
bram3->SSRA(SSR3); conv->SSR3(SSR3);
bram2->SSRA(SSR2); conv->SSR2(SSR2);
conv->addr(addr);
conv->din(din);
conv->dout(dout);
conv->r(r);
conv->w(w);
conv->clk(clk);
conv->memwait(memwait);
conv->en(en);
dbgconv = new DBGBRAM8KCONV("dbgconv");
dbgconv->DO(dbgDO);
dbgconv->ADDR(dbgADDR);
dbgconv->DI(dbgDI);
dbgconv->EN(dbgEN);
dbgconv->CLK(dbgCLK);
dbgconv->WE(dbgWE);
dbgconv->RST(dbgRST);
bram1->DOB(dDO1); dbgconv->DO1(dDO1);
bram0->DOB(dDO0); dbgconv->DO0(dDO0);
bram1->DOPB(dDOP1); dbgconv->DOP1(dDOP1);
bram0->DOPB(dDOP0); dbgconv->DOP0(dDOP0);
bram1->ADDRB(dADDR1); dbgconv->ADDR1(dADDR1);
bram0->ADDRB(dADDR0); dbgconv->ADDR0(dADDR0);
bram1->DIB(dDI1); dbgconv->DI1(dDI1);
bram0->DIB(dDI0); dbgconv->DI0(dDI0);
bram1->DIPB(dDIP1); dbgconv->DIP1(dDIP1);
bram0->DIPB(dDIP0); dbgconv->DIP0(dDIP0);
bram1->ENB(dEN1); dbgconv->EN1(dEN1);
bram0->ENB(dEN0); dbgconv->EN0(dEN0);
bram1->CLKB(dCLK1); dbgconv->CLK1(dCLK1);
bram0->CLKB(dCLK0); dbgconv->CLK0(dCLK0);
bram1->WEB(dWE1); dbgconv->WE1(dWE1);
bram0->WEB(dWE0); dbgconv->WE0(dWE0);
bram1->SSRB(dSSR1); dbgconv->SSR1(dSSR1);
bram0->SSRB(dSSR0); dbgconv->SSR0(dSSR0);
bram3->DOB(dDO3); dbgconv->DO3(dDO3);
bram2->DOB(dDO2); dbgconv->DO2(dDO2);
bram3->DOPB(dDOP3); dbgconv->DOP3(dDOP3);
bram2->DOPB(dDOP2); dbgconv->DOP2(dDOP2);
bram3->ADDRB(dADDR3); dbgconv->ADDR3(dADDR3);
bram2->ADDRB(dADDR2); dbgconv->ADDR2(dADDR2);
bram3->DIB(dDI3); dbgconv->DI3(dDI3);
bram2->DIB(dDI2); dbgconv->DI2(dDI2);
bram3->DIPB(dDIP3); dbgconv->DIP3(dDIP3);
bram2->DIPB(dDIP2); dbgconv->DIP2(dDIP2);
bram3->ENB(dEN3); dbgconv->EN3(dEN3);
bram2->ENB(dEN2); dbgconv->EN2(dEN2);
bram3->CLKB(dCLK3); dbgconv->CLK3(dCLK3);
bram2->CLKB(dCLK2); dbgconv->CLK2(dCLK2);
bram3->WEB(dWE3); dbgconv->WE3(dWE3);
bram2->WEB(dWE2); dbgconv->WE2(dWE2);
bram3->SSRB(dSSR3); dbgconv->SSR3(dSSR3);
bram2->SSRB(dSSR2); dbgconv->SSR2(dSSR2);
};
};
#endif