www.pudn.com > noc.rar > benif_network3x2.cpp

#include "benif_network3x2.h"

void BENIF_NET_WRAPPER::count()
{
  if( RST.read() ) cnt = 0;
  else cnt = cnt.read()+1;
}
void BENIF_NET_WRAPPER::register_write()
{
  sc_uint<8> reg = ADDRESS.read().range(7,0);
  if( RST.read() ) {
    addr = 0; memsel = 0; control = 0;
  }
  else if( WRITE_STROBE.read() )
    {
      switch(reg)
        {
        case 2 : memsel = DATA.read(); break;
        case 3 : addr = DATA.read(); break;
        case 4 : control = DATA.read(); break;
        }
    }

  if( (READ_STROBE.read()||WRITE_STROBE.read()) && reg==5 ) addr = addr.read()+4;
}

void BENIF_NET_WRAPPER::register_read()
{
  sc_uint<8> reg = ADDRESS.read().range(7,0);
  sc_int<32> memout;
  sc_lv<32> dout;
  sc_lv<32> z32;
  sc_uint<32> mem = memsel.read();
  for(int i=0;i<32;i++) z32[i]='z'; 

  switch( mem ){
  case 0x00000001 : memout = romDO0.read(); break;
  case 0x00000002 : memout = ramDO0.read(); break;
  case 0x00000004 : memout = romDO1.read(); break;
  case 0x00000008 : memout = ramDO1.read(); break;
  case 0x00000010 : memout = romDO2.read(); break;
  case 0x00000020 : memout = ramDO2.read(); break;
  case 0x00000040 : memout = romDO3.read(); break;
  case 0x00000080 : memout = ramDO3.read(); break;
  case 0x00000100 : memout = romDO4.read(); break;
  case 0x00000200 : memout = ramDO4.read(); break;
  case 0x00000400 : memout = romDO5.read(); break;
  case 0x00000800 : memout = ramDO5.read(); break;
#ifdef USEXRAM
  case 0x00001000 : memout = xDO0.read(); break;
  case 0x00002000 : memout = xDO1.read(); break;
  case 0x00004000 : memout = xDO2.read(); break;
  case 0x00008000 : memout = xDO3.read(); break;
  case 0x00010000 : memout = xDO4.read(); break;
  case 0x00020000 : memout = xDO5.read(); break;
#endif

  default : memout = 0;
  }
  
  switch(reg)
    {
    case 2 : dout = memsel.read(); break;
    case 3 : dout = addr.read(); break;
    case 4 : dout = control.read(); break;
    case 5 : dout = memout; break;
    case 6 : dout = pc0.read(); break;
    case 7 : dout = pc1.read(); break;
    case 8 : dout = pc2.read(); break;
    case 9 : dout = pc3.read(); break;
    case 10 : dout = pc4.read(); break;
    case 11 : dout = pc5.read(); break;

    default : dout = memout; break;
    }
    
  if( READ_STROBE.read() )
    DATA.write( dout );
  else {
    DATA.write( z32 );
  }
  
  DMA_DATA.write( z32 );
}

void BENIF_NET_WRAPPER::logic()
{
  sc_bv<4> leds;
  
  reset.write(RST.read());
  enable0.write(control.read()[0] != 0);
  enable1.write(control.read()[1] != 0);
  enable2.write(control.read()[2] != 0);
  enable3.write(control.read()[3] != 0);
  enable4.write(control.read()[4] != 0);
  enable5.write(control.read()[5] != 0);
  
  leds[3] = !(control.read()[0] != 0);
  leds[2] = !(cnt.read()[24] != 0);
  leds[1] = 1;
  leds[0] = 1;
  
  LEDS.write(leds);
  
  INT.write(false);
  DMA_REN.write(false);
  DMA_WEN.write(false);
}


void BENIF_NET_WRAPPER::memory_input()
{
  sc_uint<8> reg = ADDRESS.read().range(7,0);
  bool en = (reg==5);
  bool we = (en&&WRITE_STROBE.read());

  
#ifndef VERILOG
  memDI.write( we ? DATA.read() : 0 );
#else
  memDI.write( DATA.read() );
#endif
  romWE0.write(we && memsel.read()[0]); ramWE0.write(we && memsel.read()[1]);
  romWE1.write(we && memsel.read()[2]); ramWE1.write(we && memsel.read()[3]);
  romWE2.write(we && memsel.read()[4]); ramWE2.write(we && memsel.read()[5]);
  romWE3.write(we && memsel.read()[6]); ramWE3.write(we && memsel.read()[7]);
  romWE4.write(we && memsel.read()[8]); ramWE4.write(we && memsel.read()[9]);
  romWE5.write(we && memsel.read()[10]); ramWE5.write(we && memsel.read()[11]);

  memADDR.write( addr.read() );
  memCLK.write( IFCLK.read() );
  memEN.write(en);
  memRST.write(false);

#ifdef USEXRAM
  xADDR.write( addr.read() );
  xCLK.write( IFCLK.read() );
  xWE0.write( control.read()[31]!=0 )
  xWE1.write( control.read()[31]!=0 )
  xWE2.write( control.read()[31]!=0 )
  xWE3.write( control.read()[31]!=0 )
  xWE4.write( control.read()[31]!=0 )
  xWE5.write( control.read()[31]!=0 )
#endif
}