www.pudn.com > noc.rar > benif.h

#include 
#include "mmips.h"

SC_MODULE(BENIF_WRAPPER)
{
  sc_in< bool > IFCLK;
  sc_in< bool > WRITE_STROBE;
  sc_in< bool > READ_STROBE;
  sc_in< bool > DMA_ENABLE;
  sc_in< bool > DMA_DIRECTION;
  sc_in< bool > DMA_RDY;
  sc_in< bool > DMA_DATA_AVAILABLE;
  sc_in< bool > RST;
  sc_in< bool > SYNC_RESET;
  sc_in< bool > DMA_RESET;

  sc_in< sc_uint<31> > ADDRESS;
  sc_inout_rv< 32 > DATA;

  sc_inout_rv< 32 > DMA_DATA;
  sc_in< sc_uint<32> > COUNT;
  sc_in< sc_uint<4> > DMA_SEL;

  sc_out< bool > DMA_WEN;
  sc_out< bool > DMA_REN;
  sc_out< bool > INT;

  sc_out< sc_bv<4> > LEDS;

  sc_out > memADDR;
  sc_out > memDI;
  sc_out memEN;
  sc_out memCLK;
  sc_out memRST;
  sc_in > ramDO,romDO;
  sc_out ramWE,romWE;
  sc_in > pc;
  sc_out enable;
  sc_out reset;

  sc_signal< sc_uint<32> > addr;
  sc_signal< sc_uint<32> > memsel;
  sc_signal< sc_uint<25> > cnt;
  
  sc_signal< sc_uint<32> > control;
  
  void logic();
  void count();
  void register_write();
  void register_read();
  void memory_input();
  
  SC_CTOR(BENIF_WRAPPER)
  {
    SC_METHOD(logic);
    sensitive << IFCLK << WRITE_STROBE << READ_STROBE << DMA_ENABLE 
              << DMA_DIRECTION << DMA_RDY << DMA_DATA_AVAILABLE
              << RST << SYNC_RESET << DMA_RESET
              << ADDRESS << DATA
              << DMA_DATA << COUNT << DMA_SEL
              << control << addr << memsel << cnt;

    SC_METHOD(memory_input);
    sensitive << IFCLK << DATA << addr << memsel << ADDRESS << WRITE_STROBE << control;

    SC_METHOD(count);
    sensitive_pos << IFCLK << RST;
    
    SC_METHOD(register_write);
    sensitive_pos << IFCLK << RST;
    
    SC_METHOD(register_read);
    sensitive << READ_STROBE << ADDRESS << addr << memsel;
	sensitive << pc;
	sensitive << ramDO << romDO;
  }
};

SC_MODULE(BENIF)
{
  mMIPS *mmips;
  BENIF_WRAPPER *wrapper;

  
  sc_in   MIPSCLK;
  
  sc_in< bool > IFCLK;
  sc_in< bool > WRITE_STROBE;
  sc_in< bool > READ_STROBE;
  sc_in< bool > DMA_ENABLE;
  sc_in< bool > DMA_DIRECTION;
  sc_in< bool > DMA_RDY;
  sc_in< bool > DMA_DATA_AVAILABLE;
  sc_in< bool > RST;
  sc_in< bool > SYNC_RESET;
  sc_in< bool > DMA_RESET;

  sc_in< sc_uint<31> > ADDRESS;
  sc_inout_rv< 32 > DATA;
  sc_inout_rv< 32 > DMA_DATA;
  sc_in< sc_uint<32> > COUNT;
  sc_in< sc_uint<4> > DMA_SEL;

  sc_out< bool > DMA_WEN;
  sc_out< bool > DMA_REN;
  sc_out< bool > INT;
  sc_out< sc_bv<4> > LEDS;

  sc_signal > memADDR;
  sc_signal > memDI;
  sc_signal memEN;
  sc_signal memCLK;
  sc_signal memRST;

  sc_signal > ramDO,romDO;
  sc_signal ramWE,romWE;
  sc_signal > pc;
  sc_signal enable;
  sc_signal reset;

  
  // unused device interface
  sc_signal< sc_bv > dev_dout;
  sc_signal< sc_bv > dev_din;
  sc_signal< bool > dev_r, dev_w;
  sc_signal< bool > dev_rdyr, dev_rdyw;
  sc_signal< bool > dev_wdata, dev_waddr;
  sc_signal dev_send_eop;
  sc_signal dev_rcv_eop;


  SC_CTOR(BENIF)
  {
    mmips = new mMIPS("mMIPS");
    wrapper = new BENIF_WRAPPER("wrapper");

    wrapper->reset(reset);
    wrapper->enable(enable);
    wrapper->IFCLK(IFCLK);
    wrapper->WRITE_STROBE(WRITE_STROBE);
    wrapper->READ_STROBE(READ_STROBE);
    wrapper->DMA_ENABLE(DMA_ENABLE);
    wrapper->DMA_DIRECTION(DMA_DIRECTION);
    wrapper->DMA_RDY(DMA_RDY);
    wrapper->DMA_DATA_AVAILABLE(DMA_DATA_AVAILABLE);
    wrapper->RST(RST);
    wrapper->SYNC_RESET(SYNC_RESET);
    wrapper->DMA_RESET(DMA_RESET);
    wrapper->ADDRESS(ADDRESS);
    wrapper->DATA(DATA);
    wrapper->DMA_DATA(DMA_DATA);
    wrapper->COUNT(COUNT);
    wrapper->DMA_SEL(DMA_SEL);
    wrapper->DMA_WEN(DMA_WEN);
    wrapper->DMA_REN(DMA_REN);
    wrapper->INT(INT);
    wrapper->LEDS(LEDS);

    wrapper->memADDR(memADDR);
    wrapper->memDI(memDI);
    wrapper->memEN(memEN);
    wrapper->memCLK(memCLK);
    wrapper->memRST(memRST);
    wrapper->ramDO(ramDO);
    wrapper->ramWE(ramWE);
    wrapper->romDO(romDO);
    wrapper->romWE(romWE);

	mmips->clock(MIPSCLK); mmips->reset(reset); mmips->enable(enable);

    mmips->ramADDR(memADDR); mmips->romADDR(memADDR);
    mmips->ramDI(memDI); mmips->romDI(memDI);
    mmips->ramEN(memEN); mmips->romEN(memEN);
    mmips->ramCLK(memCLK); mmips->romCLK(memCLK);
    mmips->ramRST(memRST); mmips->romRST(memRST);
    mmips->ramDO(ramDO);
    mmips->ramWE(ramWE);
    mmips->romDO(romDO);
    mmips->romWE(romWE);

    mmips->bus_pc(pc); wrapper->pc(pc);
  
  
	mmips->dev_dout(dev_dout);
	mmips->dev_din(dev_din);
	mmips->dev_r(dev_r);
	mmips->dev_w(dev_w);
	mmips->dev_rdyr(dev_rdyr);
	mmips->dev_rdyw(dev_rdyw);
	mmips->dev_wdata(dev_wdata);
	mmips->dev_waddr(dev_waddr);
	mmips->dev_send_eop(dev_send_eop);
	mmips->dev_rcv_eop(dev_rcv_eop);

  }
};