www.pudn.com > noc.rar > bennoc.vhd

library IEEE; 
use IEEE.std_logic_1164.all; 
use ieee.numeric_std.all; 
 
entity bennoc is 
    port (	 
          -- Mips clock. 
        	MIPS_CLK: in STD_LOGIC; 
          -- Interface clock. 
        	DSP_CLK: in STD_LOGIC; 
        	-- Global reset. 
        	RSTl: in STD_LOGIC; 
        	-- Indicates whether Spartan can receive data. 
        	BUSY: in STD_LOGIC; 
        	-- Indicates whether Spartan has data to send. 
        	EMPTY: in STD_LOGIC; 
        	-- Indicates that ADIO is address or data. 
        	AS_DSl: in STD_LOGIC; 
        	-- Read/Write enable. 
        	RENl_WENl: out STD_LOGIC; 
        	-- Indicates if Spartan is being read or being written to. 
        	RDl_WR: out STD_LOGIC; 
        	-- Interrupt to Spartan. 
        	INTl: out STD_LOGIC; 
        	-- Test LEDs. 
        	LEDS: out STD_LOGIC_VECTOR (3 downto 0); 
        	-- Data IO between Spartan and Virtex. 
        	ADIO: inout STD_LOGIC_VECTOR (31 downto 0) 
    		); 
end bennoc; 
 
architecture arch of bennoc is 
 
  -- communication core 
  -- it can decode 24-bit addresses and 32 (5-bit) registers 
  component benif_32reg_24bmem is 
    port ( 
      CLK: in STD_LOGIC; 
      RSTl: in STD_LOGIC; 
      BUSY: in STD_LOGIC; 
      EMPTY: in STD_LOGIC; 
      AS_DSl: in STD_LOGIC; 
      DMA_WEN: in STD_LOGIC; 
      DMA_REN: in STD_LOGIC; 
      INT: in STD_LOGIC; 
      RENl_WENl: out STD_LOGIC; 
      RDl_WR: out STD_LOGIC; 
      INTl: out STD_LOGIC; 
      ADDRESS: out STD_LOGIC_VECTOR (30 downto 0); 
      WRITE_STROBE: out STD_LOGIC; 
      READ_STROBE: out STD_LOGIC; 
      COUNT: out STD_LOGIC_VECTOR (31 downto 0); 
      DMA_ENABLE: out STD_LOGIC; 
      DMA_DIRECTION: out STD_LOGIC; 
      DMA_SEL: out STD_LOGIC_VECTOR (3 downto 0); 
      DMA_RDY: out STD_LOGIC; 
      DMA_DATA_AVAILABLE: out STD_LOGIC; 
      RST: out STD_LOGIC; 
      SYNC_RESET: out STD_LOGIC; 
      DMA_RESET: out STD_LOGIC; 
      ADIO: inout STD_LOGIC_VECTOR (31 downto 0); 
      DATA: inout STD_LOGIC_VECTOR (31 downto 0); 
      DMA_DATA: inout STD_LOGIC_VECTOR (31 downto 0) 
      ); 
  end component; 
 
  -- Network on chip 
  component BENIF_NET is port( 
    MIPSCLK : in STD_LOGIC; 
    IFCLK : in STD_LOGIC; 
    DMA_WEN : out  STD_LOGIC; 
    DMA_REN : out  STD_LOGIC; 
    ADDRESS : in  STD_LOGIC_VECTOR (30 downto 0); 
    INT : out  STD_LOGIC; 
    WRITE_STROBE : in  STD_LOGIC;   
    READ_STROBE : in  STD_LOGIC; 
    COUNT: in  STD_LOGIC_VECTOR (31 downto 0); 
    DMA_ENABLE : in  STD_LOGIC; 
    DMA_DIRECTION : in  STD_LOGIC; 
    DMA_SEL : in  STD_LOGIC_VECTOR(3 downto 0); 
    DMA_RDY : in  STD_LOGIC; 
    DMA_DATA_AVAILABLE : in  STD_LOGIC; 
    RST : in  STD_LOGIC; 
    SYNC_RESET : in  STD_LOGIC; 
    DMA_RESET : in  STD_LOGIC; 
    DATA: inout  STD_LOGIC_VECTOR (31 downto 0); 
    DMA_DATA: inout  STD_LOGIC_VECTOR(31 downto 0); 
    LEDS : out STD_LOGIC_VECTOR(3 downto 0) 
    );   
  end component; 
 
component BUFGDLL port 
	       (I: in STD_LOGIC;  
		O: out STD_LOGIC 
		); 
end component;	 
 
  component CLKDLL 
    port ( 
      CLKIN  : in  std_logic;           -- Main Clock input 
      CLKFB  : in  std_logic;           -- Clock feedback 
      RST    : in  std_logic;           -- Reset signal 
      CLK0   : out std_logic;           -- Deskewed clock 0 phase 
      CLK90  : out std_logic;           -- Deskewed clock 90 phase 
      CLK180 : out std_logic;           -- Deskewed Clock 180 phase 
      CLK270 : out std_logic;           -- Deskewed Clock 270 phase 
      CLK2X  : out std_logic;           -- Deskewed Clock 2x 
      CLKDV  : out std_logic;           -- Deskewed Clock Divided 
      LOCKED : out std_logic);          -- Locked signal 
  end component; 
 
  component BUFG 
    port ( 
      I : in  std_logic; 
      O : out std_logic); 
  end component; 
 
  component IBUFG 
    port ( 
      I : in  std_logic; 
      O : out std_logic); 
  end component; 
 
  signal DSP_CLKi,DSP_CLKubi,DSP_CLKibufg : std_logic; 
  signal RST,RST_EXT,RST_INTl : std_logic; 
   
  signal IFCLK : STD_LOGIC; 
  signal DMA_WEN : STD_LOGIC; 
  signal DMA_REN : STD_LOGIC; 
  signal ADDRESS : STD_LOGIC_VECTOR (30 downto 0); 
  signal INT : STD_LOGIC; 
  signal WRITE_STROBE : STD_LOGIC;   
  signal READ_STROBE : STD_LOGIC; 
  signal COUNT: STD_LOGIC_VECTOR (31 downto 0); 
  signal DMA_ENABLE : STD_LOGIC; 
  signal DMA_DIRECTION : STD_LOGIC; 
  signal DMA_SEL : STD_LOGIC_VECTOR(3 downto 0); 
  signal DMA_RDY : STD_LOGIC; 
  signal DMA_DATA_AVAILABLE : STD_LOGIC; 
  signal SYNC_RESET : STD_LOGIC; 
  signal DMA_RESET : STD_LOGIC; 
  signal DATA: STD_LOGIC_VECTOR (31 downto 0); 
  signal DMA_DATA: STD_LOGIC_VECTOR (31 downto 0); 
 
begin  -- arch 
 
RST_EXT <= not(RSTl); 
 
H3 : IBUFG 
    port map( 
      I => DSP_CLK, 
      O => DSP_CLKibufg 
      ); 
 
CLK_INDLL : CLKDLL 
    port map( 
      CLKIN  => DSP_CLKibufg, 
      CLKFB  => IFCLK, 
      RST    => RST_EXT, 
      CLK0   => DSP_CLKubi, 
      CLK90  => open, 
      CLK180 => open, 
      CLK270 => open, 
      CLK2X  => open, 
      CLKDV  => open, 
      LOCKED => RST_INTl 
      ); 
 
H4 : BUFG 
    port map( 
      I => DSP_CLKubi, 
      O => IFCLK 
    ); 
 
  svif : benif_32reg_24bmem port map ( 
      -- signals from Spartan 
      CLK => IFCLK, 
      RSTl => RST_INTl, 
      BUSY => BUSY, 
      EMPTY => EMPTY, 
      AS_DSl => AS_DSl, 
      RENl_WENl => RENl_WENl, 
      RDl_WR => RDl_WR, 
      INTl => INTl, 
      ADIO => ADIO, 
      -- signals to user 
      DMA_WEN => DMA_WEN, 
      DMA_REN => DMA_REN, 
      INT => INT, 
      ADDRESS => ADDRESS, 
      WRITE_STROBE => WRITE_STROBE, 
      READ_STROBE => READ_STROBE, 
      COUNT => COUNT, 
      DMA_ENABLE => DMA_ENABLE, 
      DMA_DIRECTION => DMA_DIRECTION, 
      DMA_SEL => DMA_SEL, 
      DMA_RDY => DMA_RDY, 
      DMA_DATA_AVAILABLE => DMA_DATA_AVAILABLE, 
      RST => RST, 
      SYNC_RESET => SYNC_RESET, 
      DMA_RESET => DMA_RESET, 
      DATA => DATA, 
      DMA_DATA => DMA_DATA 
    ); 
 
   noc : BENIF_NET port map ( 
  	 MIPSCLK => MIPS_CLK,        
      IFCLK => IFCLK,        
      DMA_WEN => DMA_WEN, 
      DMA_REN => DMA_REN,							 
      INT => INT, 
      ADDRESS => ADDRESS, 
      WRITE_STROBE => WRITE_STROBE, 
      READ_STROBE => READ_STROBE, 
      COUNT => COUNT, 
      DMA_ENABLE => DMA_ENABLE, 
      DMA_DIRECTION => DMA_DIRECTION, 
      DMA_SEL => DMA_SEL, 
      DMA_RDY => DMA_RDY, 
      DMA_DATA_AVAILABLE => DMA_DATA_AVAILABLE, 
      RST => RST, 
      SYNC_RESET => SYNC_RESET, 
      DMA_RESET => DMA_RESET, 
      DATA => DATA, 
      DMA_DATA => DMA_DATA, 
	 LEDS => LEDS 
    );   
 
end arch;