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//====================================================================
// File Name : 2410iis.c
// Function : S3C2410 IIS (UDA1341) Record & Play Test Program
// (DMA2, Double Buffer, Record, Play)
// Program : Shin, On Pil (SOP)
// Date : October 01, 2002
// Version : 0.0
// History
// 0.0 : Programming start (March 06, 2002) -> SOP
// 0.1 : Added Slave mode Test Program(July 24, 2002) -> KWT(Tark), SOP
// Optimization (December 09, 2002) -> SOP
//====================================================================
#include "2410addr.h"
#include "2410lib.h"
#include "def.h"
#include "2410iis.h"
//#include "sglib.h"
void ChangeDMA2(void);
void IIS_PortSetting(void);
void __irq DMA2_Done(void);
//#define PLAY 0
//#define RECORD 1
#define PollMode 0 //1: Polling Mode
//#define DMA2Mode 1 //1: DMA2 Mode
unsigned char *Buf,*_temp;
volatile unsigned int size = 0;
volatile unsigned int fs = 0;
volatile char which_Buf = 1;
unsigned short *txdata;
//------------------------------------------------------------------------------
// SMDK2410 IIS Configuration
// GPB4 = L3CLOCK, GPB3 = L3DATA, GPB2 = L3MODE
// GPE4 = I2SSDO, GPE3 = I2SSDI, GPE2 = CDCLK, GPE1 = I2SSCLK, GPE0 = I2SLRCK
//------------------------------------------------------------------------------
//*********************[ Test_Iis ] *********************************
void Test_Iis(void)
{
unsigned int i;
// Uart_TxEmpty(0);
txdata = (unsigned short *)0x30080000;
// txdata = (unsigned short *)0x08000000;
ChangeClockDivider(1,1); //1:2:4
ChangeMPllValue(0x96,0x5,0x1); //FCLK=135.428571MHz (PCLK=33.857142MHz)
Uart_Init(33857142,115200);
Uart_Printf("[ IIS test (Play) using MXIC MX92U832 CODEC ]\n");
// save_B = rGPBCON;
// save_E = rGPECON;
// save_PB = rGPBUP;
// save_PE = rGPEUP;
IIS_PortSetting();
// pISR_DMA2 = (unsigned)DMA2_Done;
// rINTMSK &= ~(BIT_DMA2);
Buf = (unsigned char *)0x30080000;
// Buf = (unsigned char *)0x08000000;
i=0;
while(1)
{
if((*(Buf + i) == 'd') && (*(Buf + i + 1) == 'a') && (*(Buf + i + 2) == 't') && (*(Buf + i + 3) == 'a'))
{
i += 4;
break;
}
i++;
}
size = *(Buf + i) | *(Buf + i + 1)<<8 | *(Buf + i + 2)<<16 | *(Buf + i + 3)<<24;
size = (size>>1)<<1;
fs = *(Buf + 0x18) | *(Buf + 0x19)<<8 | *(Buf + 0x1a)<<16 | *(Buf + 0x1b)<<24;
i += 4;
Uart_Printf("Sample Size = 0x%x\n",size/2);
Uart_Printf("Sampling Frequency = %d Hz\n",fs);
Uart_Printf("\n[ Now play the wave file .....]\n");
// MXIC SG Initial IIS
// mx_SG_DeviceControl(MX_POWERMANAGEMENT,0x01,0,0);//set Power On
// mx_SG_DeviceControl(MX_ANALOG_SWITCH,0x90,0,0);//set Analog Switch, Enable HP And SP
// Delay(500);
// mx_SG_DeviceControl(MX_HP_VOLUME,0x0,0x1f,0x1f);//set HP Volume
// mx_SG_DeviceControl(MX_SP_VOLUME,0x1f,0,0);//set SP Volume
// SGWrite(0x76,0x0c);
#ifdef DMA2Mode
//DMA2 Initialize
// rDISRC2 = (int)(Buf + 0x30); //0x31000030~(Remove header)
rDISRC2 = (int)(Buf + i); //0x31000030~(Remove header)
rDISRCC2 = (0<<1) + (0<<0); //The source is in the system bus(AHB), Increment
rDIDST2 = ((U32)IISFIFO); //IISFIFO
rDIDSTC2 = (1<<1) + (1<<0); //The destination is in the peripheral bus(APB), Fixed
rDCON2 = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(0<<24)+(1<<23)+(0<<22)+(1<<20)+(size/4);
//1010 0000 1001 xxxx xxxx xxxx xxxx xxxx
//Handshake[31], Sync PCLK[30], CURR_TC Interrupt Request[29], Single Tx[28], Single service[27],
//I2SSDO[26:24], DMA source selected[23],Auto-reload[22], Half-word[21:20], size/2[19:0]
rDMASKTRIG2 = (0<<2) + (1<<1) + (0<<0); //No-stop[2], DMA2 channel On[1], No-sw trigger[0]
#endif
//IIS Initialize
if(fs==44100) //11.2896MHz(256fs)
rIISPSR = (2<<5) + 2; //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4) 33868800HZ
else if(fs == 22050) //fs=22050, 5.6448MHz(256fs)
rIISPSR = (5<<5) + 5; //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)
else if(fs == 8000)
{
ChangeClockDivider(1,1); //1:2:4
ChangeMPllValue(0xa4,0x5,0x1); //FCLK=147.428571MHz (PCLK=36.85MHz)
Uart_Init(36850000,115200);
rIISPSR = (17<<5) + 17; //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)
}
else if(fs == 11025)
rIISPSR = (11<<5) + 11; //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)
else if(fs == 16000)
{
ChangeClockDivider(1,1); //1:2:4
ChangeMPllValue(0xa4,0x5,0x1); //FCLK=147MHz (PCLK=36.85MHz)
Uart_Init(36850000,115200);
rIISPSR = (8<<5) + 8; //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)
}
else if(fs == 32000)
{
ChangeClockDivider(1,1); //1:2:4
ChangeMPllValue(0xb7,0x5,0x1); //FCLK=163.714825MHz (PCLK=40.928571MHz)
Uart_Init(40928571,115200);
rIISPSR = (4<<5) + 4; //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)
}
else if(fs == 48000)
{
ChangeClockDivider(1,1); //1:2:4
ChangeMPllValue(0xa4,0x5,0x1); //FCLK=147MHz (PCLK=36.85MHz)
Uart_Init(36850000,115200);
rIISPSR = (2<<5) + 2; //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)
}
#ifdef DMA2Mode
rIISCON = (1<<5) + (1<<2) + (1<<1); //Tx DMA enable[5], Rx idle[2], Prescaler enable[1]
//Master mode[8],Tx mode[7:6],High for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0]
rIISMOD = (0<<8) + (2<<6) + (1<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
rIISFCON = (1<<15) + (1<<13); //Tx DMA,Tx FIFO --> start piling....
Uart_Printf("\nPress any key to exit!!!\n");
//IIS Tx Start
rIISCON |= 0x1; //IIS Interface start
while(!Uart_GetKey());
{
if((rDSTAT2 & 0xfffff) < (size/6))
ChangeDMA2();
}
#endif
#ifdef PollMode
//IIS Initialize
//Master mode[8],Tx mode[7:6],High for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0]
rIISMOD = (0<<8) + (2<<6) + (1<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
rIISFCON = (0<<15) + (1<<13); //Tx Normal[15],Tx FIFO Enable[13] --> start piling....
//Tx DMA disable[5],Rx DMA disable[4],Tx not idle[3],Rx idle[2],prescaler enable[1],stop[0]
rIISCON = (0<<5) + (0<<4) + (0<<3) + (1<<2) + (1<<1) + (0<<0);
//Tx start
rIISCON |=0x1;
txdata = (unsigned short *)(0x30080000 + i);
// txdata = (unsigned short *)(0x08000000 + i);
// for(i=0;i<(size/2);i++)
// {
// while( (rIISCON & 0x080) == 0x80 ); //wait when fifo is not empty.
// *IISFIFO = *(txdata+i); // put the data into fifo
// }
#endif
}
//===================================================================
void ChangeDMA2(void)
{
if(which_Buf)
{
rDISRCC2 = (0<<1) + (0<<0); //AHB, Increment
rDISRC2 = (int)(Buf + 0x30); //0x31000030~(Remove header)
}
else
{
rDISRCC2 = (0<<1) + (0<<0); //AHB, Increment
rDISRC2 = (int)(Buf + 0x30+(size/2)); //0x31000030 + size/2~
}
}
//===================================================================
void IIS_PortSetting(void)
{
//----------------------------------------------------------
// PORT F GROUP
//Ports : GPF6 GPF5 GPF4 GPF3
//Signal : EINT6 EINT5 EINT4 EINT3
//Setting: RESERVE RESERVE RESERVE RESERVE
//Binary : 11 , 11 11 11
//----------------------------------------------------------
// rGPFUP = rGPFUP & ~(0xf<<3 | (0xf<<3); //The pull up function is disabled GPF[6:3]
// rGPFCON = rGPfCON & ~(0x3f<<6) | (0x15<<6);
//----------------------------------------------------------
// PORT E GROUP
//Ports : GPE4 GPE3 GPE2 GPE1 GPE0
//Signal : I2SSDO I2SSDI CDCLK I2SSCLK I2SLRCK
//Binary : 10 , 10 10 , 10 10
//----------------------------------------------------------
rGPEUP = rGPEUP & ~(0x1f) | 0x1f; //The pull up function is disabled GPE[4:0] 1 1111
rGPECON = rGPECON & ~(0x3ff) | 0x2aa; //GPE[4:0]=I2SSDO:I2SSDI:CDCLK:I2SSCLK:I2SLRCK
// rGPFUP = ((rGPFUP & ~(1<<0)) | (1<<0)); //GPF0
// rGPFCON = ((rGPFCON & ~(3<<0)) | (1<<1)); //GPF0=EINT0
// rEXTINT0 = ((rEXTINT0 & ~(7<<0)) | (2<<0)); //EINT0=falling edge triggered
}
//===================================================================
//===================================================================
void __irq DMA2_Done(void)
{
ClearPending(BIT_DMA2); //Clear pending bit
//Uart_Printf("DMA\n");
WrUTXH0('@');
if(!which_Buf)
which_Buf = 1;
else
which_Buf = 0;
}
extern unsigned char MIDI_flg;
void IIS_Polling(void)
{
unsigned int i;
for(i=0;i<(size/2);i++)
{
if(MIDI_flg != 2)
break;
while( (rIISCON & 0x080) == 0x80 ); //wait when fifo is not empty.
*IISFIFO = *(txdata+i); // put the data into fifo
}
}