www.pudn.com > Demo C.rar > sysLib.c
/* sysLib.c - system-dependent library */
/* Copyright 1984-2001 Wind River Systems, Inc. */
/*
modification history
--------------------
01d,24sep01,g_h move SIO, TIMER, EEPROM driver to be localy
01c,07may01,g_h add support for visionWARE 2.00
01d,21oct99,elk fixed system hang sysToMonitor() when using ^X to reboot
01c,19aug99,elk added local bus SDRAM and 4Mb/2Mb flash in sysPhysMemDesc.
01b,19apr99,elk added support for Ethernet.
01a,05mar99,elk adopted from estMDP8xx/sysLib.c
*/
#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "stdio.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/mmu603Lib.h"
#include "private/vmLibP.h"
#include "drv/mem/m8260Siu.h"
#include "drv/intrCtl/m8260IntrCtl.h"
#include "drv/parallel/m8260IOPort.h"
#include "m8260Pci.h"
#ifdef INCLUDE_REAL_TIME_CLOCK
#include "realClk.h"
#endif
/*add by yuecode*/
#include "flash.h"
#include "wrSbc8260.h"
/* Global data */
/*
* sysBatDesc[] is used to initialize the block address translation (BAT)
* registers within the PowerPC 603/604 MMU. BAT hits take precedence
* over Page Table Entry (PTE) hits and are faster. Overlap of memory
* coverage by BATs and PTEs is permitted in cases where either the IBATs
* or the DBATs do not provide the necessary mapping (PTEs apply to both
* instruction AND data space, without distinction).
*
* The primary means of memory control for VxWorks is the MMU PTE support
* provided by vmLib and cacheLib. Use of BAT registers will conflict
* with vmLib support. User's may use BAT registers for i/o mapping and
* other purposes but are cautioned that conflicts with caching and mapping
* through vmLib may arise. Be aware that memory spaces mapped through a BAT
* are not mapped by a PTE and any vmLib() or cacheLib() operations on such
* areas will not be effective, nor will they report any error conditions.
*
* Note: BAT registers CANNOT be disabled - they are always active.
* For example, setting them all to zero will yield four identical data
* and instruction memory spaces starting at local address zero, each 128KB
* in size, and each set as write-back and cache-enabled. Hence, the BAT regs
* MUST be configured carefully.
*
* With this in mind, it is recommended that the BAT registers be used
* to map LARGE memory areas external to the processor if possible.
* If not possible, map sections of high RAM and/or PROM space where
* fine grained control of memory access is not needed. This has the
* beneficial effects of reducing PTE table size (8 bytes per 4k page)
* and increasing the speed of access to the largest possible memory space.
* Use the PTE table only for memory which needs fine grained (4KB pages)
* control or which is too small to be mapped by the BAT regs.
*
* The BAT configuration for 4xx/6xx-based PPC boards is as follows:
* All BATs point to PROM/FLASH memory so that end customer may configure
* them as required.
*
* [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
*/
/*#define INCLUDE_LOCAL_BUS_SDRAM*/ /*hy add*/
UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
{
/* use IBAT0 to map flash execution space */
((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP),
((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT ),
/* Contrary to the misguided comments above, the other IBATS are being disabled here.... */
0, 0, /* I BAT 1 */
0, 0, /* I BAT 2 */
0, 0, /* I BAT 3 */
/* use DBAT0 to map flash into data space */
((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP),
((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT),
/* use DBAT1 to map CPM DPRAM and internal registers into data space */
/* NOTE! the internal space cannot be cached and should be guarded */
((INTERNAL_MEM_MAP_ADDR & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K | _MMU_UBAT_VS | _MMU_UBAT_VP),
((INTERNAL_MEM_MAP_ADDR & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
/* use DBAT2 to map local bus SDRAM into data space -- if user wants it */
/* NOTE! the local bus SDRAM cannot be cached -- period */
0, 0, /* D BAT 2 */
/* Contrary to the misguided comments above, DBAT3 is being disabled here.... */
0, 0, /* D BAT 3 */
};
/*
* sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
* used by the MMU to translate addresses with single page (4k) granularity.
* PTE memory space should not, in general, overlap BAT memory space but
* may be allowed if only Data or Instruction access is mapped via BAT.
*
* PTEs are held, strangely enough, in a Page Table. Page Table sizes are
* integer powers of two based on amount of memory to be mapped and a
* minimum size of 64KB. The MINIMUM recommended Page Table sizes
* for 32-bit PowerPCs are:
*
* Total mapped memory Page Table size
* ------------------- ---------------
* 8 Meg 64 K
* 16 Meg 128 K
* 32 Meg 256 K
* 64 Meg 512 K
* 128 Meg 1 Meg
* . .
* . .
* . .
*
* [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
*/
PHYS_MEM_DESC sysPhysMemDesc [] =
{
/* The following maps the Vector Table and Interrupt Stack */
{
(void *) LOCAL_MEM_LOCAL_ADRS,
(void *) LOCAL_MEM_LOCAL_ADRS,
RAM_LOW_ADRS,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
},
/* The following maps the Local SDRAM 64MB*/
{
(void *) RAM_LOW_ADRS,
(void *) RAM_LOW_ADRS,
LOCAL_MEM_SIZE - RAM_LOW_ADRS,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE | VM_STATE_MEM_COHERENCY
},
/* The following maps the FLASH on CS0 to its actual physical address and size */
{
(void *) CS0_FLASH_ADRS,
(void *) CS0_FLASH_ADRS,
CS0_FLASH_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
},
/* The following maps the flash on CS4, CS5 to its actual physical address and size */
{
(void *) FLASH_BASE_ADRS,
(void *) FLASH_BASE_ADRS,
FLASH_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
},
/* Remap */
{
(void *) 0x30000000,
(void *) 0x30000000,
0x2000000,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
} ,
{
(void *) 0x40000000,
(void *) 0x40000000,
0x2000000,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT | VM_STATE_GUARDED
}
};
int sysPhysMemDescNumEnt = NELEMENTS( sysPhysMemDesc ) ;
int sysBus = BUS ; /* system bus type (NONE) */
int sysCpu = CPU ; /* system CPU type (PPC8260) */
char *sysBootLine = BOOT_LINE_ADRS ; /* address of boot line */
char *sysExcMsg = EXC_MSG_ADRS ; /* catastrophic message area */
BOOL sysVmeEnable = FALSE ; /* by default no VME */
/* */
int sysProcNum ; /* processor number of this CPU */
int sysFlags ; /* boot flags */
char sysBootHost[ BOOT_FIELD_LEN ] ; /* name of host from which we booted */
char sysBootFile[ BOOT_FIELD_LEN ] ; /* name of file from which we booted */
/*IMPORT unsigned char glbEnetAddr [];*/
unsigned char glbEnetAddr [MAC_ADRS_LEN] = ETHERNET_MAC_ADRS; /*add by yuecode*/
/*
IMPORT unsigned char glbEnetAddr1[];
IMPORT unsigned char glbEnetAddr2 [];
*/
/* 8260 Reset Configuration Table (From page 9-2 in Rev0 of 8260 book) */
#define END_OF_TABLE 0
struct config_parms {
UINT32 inputFreq; /* MODCK_H */
UINT8 modck_h; /* | */
UINT8 modck13; /* |MODCK[1-3] */
UINT32 cpmFreq; /* Input | | CPM Core */
UINT32 coreFreq; /* | | | | | */
} modckH_modck13[] = {/* V V V V V */
{FREQ_33MHZ, 1, 0, FREQ_66MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 1, 1, FREQ_66MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 1, 2, FREQ_66MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 1, 3, FREQ_66MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 1, 4, FREQ_66MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 1, 5, FREQ_100MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 1, 6, FREQ_100MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 1, 7, FREQ_100MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 2, 0, FREQ_100MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 2, 1, FREQ_100MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 2, 2, FREQ_133MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 2, 3, FREQ_133MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 2, 4, FREQ_133MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 2, 5, FREQ_133MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 2, 6, FREQ_133MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 2, 7, FREQ_166MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 3, 0, FREQ_166MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 3, 1, FREQ_166MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 3, 2, FREQ_166MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 3, 3, FREQ_166MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 3, 4, FREQ_200MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 3, 5, FREQ_200MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 3, 6, FREQ_200MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 3, 7, FREQ_200MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 4, 0, FREQ_200MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 5, 5, FREQ_133MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 5, 6, FREQ_133MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 5, 7, FREQ_133MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 6, 0, FREQ_133MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 6, 1, FREQ_133MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 6, 2, FREQ_133MHZ, FREQ_300MHZ},
{FREQ_66MHZ, 6, 3, FREQ_166MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 6, 4, FREQ_166MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 6, 5, FREQ_166MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 6, 6, FREQ_166MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 6, 7, FREQ_166MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 7, 0, FREQ_166MHZ, FREQ_300MHZ},
{FREQ_66MHZ, 7, 1, FREQ_200MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 7, 2, FREQ_200MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 7, 3, FREQ_200MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 7, 4, FREQ_200MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 7, 5, FREQ_200MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 7, 6, FREQ_200MHZ, FREQ_300MHZ},
{FREQ_66MHZ, 7, 7, FREQ_233MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 8, 0, FREQ_233MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 8, 1, FREQ_233MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 8, 2, FREQ_233MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 8, 3, FREQ_233MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 8, 4, FREQ_233MHZ, FREQ_300MHZ},
{END_OF_TABLE,0,0,0,0}
};
/* Forward function references */
UINT32 vxImmrGet (void);
void vxImmrSet (UINT32 value);
void sysClkRateAdjust ( int * );
UINT32 sysChipRev(void);
void sysCpmReset(void);
UINT8 sysUserSwitchGet(void);
UINT32 sysCoreFreqGet(void);
UINT32 sysCpmFreqGet(void);
UINT32 sysInputFreqGet(void);
UINT8 sysModck13Get (void);
UINT8 sysModckHGet (void);
/* locals */
LOCAL UINT32 immrAddress = (UINT32) INTERNAL_MEM_MAP_ADDR;
/* Additional Components */
#if (NV_RAM_SIZE == NONE)
#include "mem/nullNvRam.c"
#else
/*#include "eeprom.c"*/ /*zsc move it*/
#include "mem/byteNvRam.c"
#endif
#ifdef INCLUDE_TFFS
#include "sysTffs.c"
#endif /* INCLUDE_TFFS */
#include "sys82xxDpramLib.c"
#include "sysSerial.c"
/*#include "sysSerialScc.c"*/
#include "m8260IntrCtl.c"
#include "m8260Timer.c"
/*#include "sysLed.c"*/
#include "sysIOPort.c"
#ifdef INCLUDE_CACHE_SUPPORT
#include "sysCacheLockLib.c"
#endif /* INCLUDE_CACHE_SUPPORT */
#ifdef INCLUDE_NETWORK
/*
#include "sysNet.h"
#include "sysNet.c"
*/ /*remove by yuecode*/
#ifdef INCLUDE_MOT_FCC
#include "sysMotFccEnd.c"
#endif /* INCLUDE_MOT_FCC */
/*
#ifdef INCLUDE_MOT_SCC
#include "sysMotSccEnd.c"
#endif
*/
/* INCLUDE_MOT_SCC */
#endif /* INCLUDE_NETWORK */
/*
#ifdef INCLUDE_VWARE_LAUNCH
#include "sysVware.c"
#endif
*/ /*yuecode*/
/* INCLUDE_VWARE_LAUNCH */
#ifdef INCLUDE_REAL_TIME_CLOCK
#include "realClk.c"
#endif
void RunLed(UINT8 mode)
{
UINT32 tmp = 0;
UINT8 how, t;
t = ((mode & 0x04) << 1) | ((mode & 0x08) >> 1)
| ((mode & 0x02) >> 1) | ((mode & 0x01) << 1) ;
how = (~t) & 0x0f;
tmp |= (how&0x0c) << 28;
tmp |= (how&0x03) << 8;
*(UINT32 *)(0x0f010d10) = tmp;
/*for(tmp = 0; tmp < 100000; tmp++);*/
}
/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/
char * sysModel( void )
{
return( "XPC8260 PowerQUICC II " ) ;
}
/*******************************************************************************
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.1/0. BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/
char * sysBspRev( void )
{
return( BSP_VERSION BSP_REV );
}
/******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various feature of the EST MPC8260 board. It sets
* up the control registers, initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*/
void sysHwInit( void )
{
volatile UINT32 temp;
int ix, i;
unsigned long *pDPRAM1;
#ifdef INCLUDE_VWARE_LAUNCH
char vwareMacAdrs[VWARE_MAC_ADRS_LEN];
#endif /* INCLUDE_VWARE_LAUNCH */
/* Get the physical location of the IMMR register */
int immrVal = vxImmrGet() ;
/* load ethernet Macaddress from flash ,and write to globe variable array: sysFecEnetAddr[],*/
/*if mac is changed, load new mac address,otherwise use default mac address:ETHERNET_MAC_ADRS*/
/*is 0x0008d200 or other any value.*/
if( *(UINT16 *)(PARA_BASE_ADRS + PARA_MACADRS_OFFSET) != 0xffff )
{
#ifdef INCLUDE_MOT_FCC
bcopy ((char *) (PARA_BASE_ADRS + PARA_MACADRS_OFFSET), (char *) glbEnetAddr, sizeof (glbEnetAddr));
#endif
}
RunLed(0x0);
/* Issue a Software Reset Command to the CPM core */
sysCpmReset();
/* Initialize the LEDs */
/*sysLedInit();*/
/* Initialize DPRAM1 to zero. */
pDPRAM1 = (unsigned long *)immrVal;
for (ix = 0; ix < 0x1000; ix++)
*pDPRAM1++ = 0;
/* reset port A, B, C, and D */
* M8260_IOP_PADIR(immrVal) = 0x00000000;
* M8260_IOP_PAPAR(immrVal) = 0x00000000;
* M8260_IOP_PASO(immrVal) = 0x00000000;
* M8260_IOP_PAODR(immrVal) = 0x00000000;
* M8260_IOP_PADAT(immrVal) = 0x00000000;
* M8260_IOP_PBDIR(immrVal) = 0x00000000;
* M8260_IOP_PBPAR(immrVal) = 0x00000000;
* M8260_IOP_PBSO(immrVal) = 0x00000000;
* M8260_IOP_PBODR(immrVal) = 0x00000000;
* M8260_IOP_PBDAT(immrVal) = 0x00000000;
* M8260_IOP_PCDIR(immrVal) = 0x00000000;
* M8260_IOP_PCPAR(immrVal) = 0x00000000;
* M8260_IOP_PCSO(immrVal) = 0x00000000;
* M8260_IOP_PCODR(immrVal) = 0x00000000;
* M8260_IOP_PCDAT(immrVal) = 0x00000000;
* M8260_IOP_PDDIR(immrVal) = 0x00000000;
* M8260_IOP_PDPAR(immrVal) = 0x00000000;
* M8260_IOP_PDSO(immrVal) = 0x00000000;
* M8260_IOP_PDODR(immrVal) = 0x00000000;
* M8260_IOP_PDDAT(immrVal) = 0x00000000;
* M8260_PCI_BR0(immrVal) = 0x30000001;
* M8260_PCI_MSK0(immrVal) = 0xfe000000;
* M8260_PCI_BR1(immrVal) = 0x40000001;
* M8260_PCI_MSK1(immrVal) = 0xfe000000;
/*
* Initialize SICR.
*/
*M8260_SICR( immrVal ) = 0x00000000;
for(i = 0; i < 1000000; i++);
/*
* Initialize interrupts - default interrupt level.
*/
m8260IntrInit() ;
*M8260_IOP_PADIR( immrVal ) |= (PA7|PA8);
for(i = 0; i < 1000000; i++);
if (sysChipRev() == SILICON_REV_PREA1)
{
temp = *M8260_SIUMCR( immrVal );
temp &= 0xf3ffffff; /* First clear DPPC ... */
temp |= 0x08000000; /* ... then enable TBEN. */
*M8260_SIUMCR( immrVal ) = temp;
}
for(i = 0; i < 1000000; i++);
/*
* Init the DPRAM lib
*/
sys82xxDpramLibInit();
for(i = 0; i < 1000000; i++);
/*
* Setup port D for SMC1.
*/
*M8260_IOP_PDPAR( immrVal ) |= (PD8 | PD9);
*M8260_IOP_PDDIR( immrVal ) |= PD9;
/*LEDs*/
/*
* Reset serial channels.
*/
sysSerialHwInit();
#ifdef FORCE_DEFAULT_BOOT_LINE
strncpy(sysBootLine,DEFAULT_BOOT_LINE,strlen(DEFAULT_BOOT_LINE)+1);
#elif defined INCLUDE_VWARE_LAUNCH
#endif /* FORCE_DEFAULT_BOOT_LINE */
/* make sure Ethernet is disabled */
/*
#ifdef INCLUDE_MOT_SCC
sysSccEnetDisable ( 0 ) ;
sysSccEnetIntDisable( 0 ) ;
#endif
*/ /*move by yuecode*//* INCLUDE_MOT_SCC */
#ifdef INCLUDE_MOT_FCC
sysFccEnetDisable (immrVal, 1);
sysFccEnetDisable (immrVal, 3);
#endif /* INCLUDE_MOT_FCC */
#ifdef INCLUDE_REAL_TIME_CLOCK
initRealTimeClk(7);
#endif
}
/*******************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* Normally, the user specifies the amount of physical memory with the
* macro LOCAL_MEM_SIZE in config.h. BSPs that support run-time
* memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined.
* If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the
* true size of physical memory.
*
* NOTE: Do no adjust LOCAL_MEM_SIZE to reserve memory for application
* use. See sysMemTop() for more information on reserving memory.
*
* RETURNS: The address of the top of physical memory.
*
* SEE ALSO: sysMemTop()
*/
char * sysPhysMemTop( void )
{
static char * physTop = NULL;
if (physTop == NULL)
{
physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);
}
return( physTop ) ;
}
/*******************************************************************************
*
* sysMemTop - get the address of the top of VxWorks memory
*
* This routine returns a pointer to the first byte of memory not
* controlled or used by VxWorks.
*
* The user can reserve memory space by defining the macro USER_RESERVED_MEM
* in config.h. This routine returns the address of the reserved memory
* area. The value of USER_RESERVED_MEM is in bytes.
*
* RETURNS: The address of the top of VxWorks memory.
*/
char *sysMemTop( void )
{
static char * memTop = NULL;
if ( memTop == NULL )
{
memTop = sysPhysMemTop() - USER_RESERVED_MEM ;
}
return memTop ;
}
/******************************************************************************
*
* sysToMonitor - transfer control to the ROM monitor
*
* This routine transfers control to the ROM monitor. Normally, it is called
* only by reboot()--which services ^X--and by bus errors at interrupt level.
* However, in some circumstances, the user may wish to introduce a
* to enable special boot ROM facilities.
*
* RETURNS: Does not return.
*/
STATUS sysToMonitor
(
int startType /* parameter passed to ROM to tell it how to boot */
)
{
FUNCPTR pRom = (FUNCPTR) (ROM_TEXT_ADRS + 4); /* Warm reboot */
#ifdef INCLUDE_MOT_FCC
/* */
/* Get the physical location of the IMMR register */
/* */
int immrVal = vxImmrGet() ;
#endif /* INCLUDE_MOT_FCC */
intLock();
cacheDisable(INSTRUCTION_CACHE);
cacheDisable(DATA_CACHE);
#if defined(INCLUDE_AUX_CLK) || defined(INCLUDE_AUXCLK)
sysAuxClkDisable();
#endif /* INCLUDE_AUX_CLK || INCLUDE_AUXCLK */
#ifdef INCLUDE_MOT_SCC
sysSccEnetDisable( 0 ); /* disable the ethernet device */
sysSccEnetIntDisable( 0 ); /* disable the ethernet device interrupt */
#endif /* INCLUDE_MOT_SCC */
#ifdef INCLUDE_MOT_FCC
/* disable the FCC */
sysFccEnetDisable (immrVal, 1);
#endif /* INCLUDE_MOT_FCC */
sysSerialReset(); /* reset the serial device */
vxMsrSet(0);
(*pRom) (startType); /* jump to bootrom entry point */
return( OK ); /* in case we continue from ROM monitor */
}
/******************************************************************************
*
* sysHwInit2 - initialize additional system hardware
*
* This routine connects system interrupt vectors and configures any
* required features not configured by sysHwInit().
*
* RETURNS: N/A
*/
void sysHwInit2 (void)
{
static BOOL configured = FALSE ;
if ( ! configured )
{
#if defined(INCLUDE_AUXCLK) || defined(INCLUDE_AUXCLK)
/*
* initialize and start auxiliary clock support
*/
sysAuxClkEnable();
#endif /* INCLUDE_AUXCLK */
/*
* initialize serial interrupts
*/
sysSerialHwInit2() ;
/*
* Indicate we have been through this procedure for reentrancy.
*/
configured = TRUE ;
}
}
/******************************************************************************
*
* sysProcNumGet - get the processor number
*
* This routine returns the processor number for the CPU board, which is
* set with sysProcNumSet().
*
* RETURNS: The processor number for the CPU board.
*
* SEE ALSO: sysProcNumSet()
*/
int sysProcNumGet( void )
{
return( sysProcNum );
}
/******************************************************************************
*
* sysProcNumSet - set the processor number
*
* This routine sets the processor number for the CPU board. Processor numbers
* should be unique on a single backplane. It also maps local resources onto
* the VMEbus.
*
* RETURNS: N/A
*
* SEE ALSO: sysProcNumGet()
*
*/
void sysProcNumSet
(
int procNum /* processor number */
)
{
sysProcNum = procNum;
}
/*******************************************************************************
*
* vxImmrSet - Set the IMMR to a specific value
*
* This routine sets the IMMR to a specific value
*
* RETURNS: N/A
*/
void vxImmrSet (UINT32 value)
{
immrAddress = value;
return;
}
/*******************************************************************************
*
* vxImmrGet - return the current IMMR value
*
* This routine returns the current IMMR value
*
* RETURNS: current IMMR value
*
*/
UINT32 vxImmrGet (void)
{
return (immrAddress);
}
/*******************************************************************************
*
* sysBaudClkFreq - returns the frequency of the BRG clock
*
* This routine returns the frequency of the BRG clock
*
* NOTE: From page 9-5 in Rev0 of 8260 book
*
* baud clock = 2*cpm_freq/2^2*(DFBRG+1) where DFBRG = 01
* = 2*cpm_freq/16
*
* RETURNS: Frequence in HZ
*
*/
int sysBaudClkFreq(void)
{
UINT32 cpmFreq = sysCpmFreqGet();
if (cpmFreq == ERROR)
return ERROR;
else
return cpmFreq*2/16;
}
/*******************************************************************************
*
* sysClkRateAdjust - calculates proper decrementer frequency for a cpu frequency
*
* This routine calculates proper decrementer frequency for a cpu frequency
*
* RETURNS: Speed in Hz
*
*/
void sysClkRateAdjust
(
int *sysDecClkFrequency
)
{
*sysDecClkFrequency = sysInputFreqGet() / DEC_ADJUSTMENT;
return;
}
/*******************************************************************************
*
* sysInputFreqGet - determines the Input Oscillator clock frequency
*
* This routine determines the Input Oscillator clock frequency
*
* NOTE: From page 9-2 in Rev0 of 8260 book
*
* RETURNS: Input frequency in HZ
*
*/
UINT32 sysInputFreqGet
(
void
)
{
#ifdef HARDCODED_FREQ_PARMS
return INPUT_FREQUENCY;
#else
UINT8 *pModck_H = (UINT8 *)HRDW_CONFIG_BYTE4;
*pModck_H &= MODCK_H_MASK; /* Mask the uper 4 bit */
switch( *pModck_H )
{
case 1: case 2: case 3: case 4:
return FREQ_33MHZ;
case 5: case 6: case 7: case 8:
return FREQ_66MHZ;
default:
return ERROR;
}
#endif /* HARDCODED_FREQ_PARMS */
}
/*******************************************************************************
*
* sysCpmFreqGet - determines the CPM operating frequency
*
* This routine determines the CPM operating frequency
*
* NOTE: From page 9-2 in Rev0 of 8260 book
*
* RETURNS: CPM frequency in HZ
*
*/
UINT32 sysCpmFreqGet
(
void
)
{
#ifdef HARDCODED_FREQ_PARMS
return CPM_FREQUENCY;
#else
UINT n;
UINT32 modck_H = sysModckHGet();
UINT32 modck13 = sysModck13Get();
for (n=0; modckH_modck13[n].coreFreq != END_OF_TABLE ;n++)
{
if ((modckH_modck13[n].modck_h == modck_H) &&
(modckH_modck13[n].modck13 == modck13))
{
return modckH_modck13[n].cpmFreq;
}
}
return ERROR;
#endif /* HARDCODED_FREQ_PARMS */
}
/*******************************************************************************
*
* sysCoreFreqGet - determines the Core operating frequency
*
* This routine determines the Core operating frequency
*
* NOTE: From page 9-2 in Rev0 of 8260 book
*
* RETURNS: Core frequency in HZ
*
*/
UINT32 sysCoreFreqGet
(
void
)
{
#ifdef HARDCODED_FREQ_PARMS
return CORE_FREQUENCY;
#else
UINT n;
UINT32 modck_H = sysModckHGet();
UINT32 modck13 = sysModck13Get();
for (n=0; modckH_modck13[n].coreFreq != END_OF_TABLE ;n++)
{
if ((modckH_modck13[n].modck_h == modck_H) &&
(modckH_modck13[n].modck13 == modck13))
{
return modckH_modck13[n].coreFreq;
}
}
return ERROR;
#endif /* HARDCODED_FREQ_PARMS */
}
/*******************************************************************************
*
* sysModckHGet - determines the value of MODCK_H reset configuration value
*
* This routine determines the value of MODCK_H reset configuration value
*
* NOTE: From page 9-2 in Rev0 of 8260 book
*
* RETURNS: MODCK_H value
*
*/
UINT8 sysModckHGet
(
void
)
{
UINT8 *pModck_H = (UINT8 *)HRDW_CONFIG_BYTE4;
*pModck_H &= MODCK_H_MASK; /* Mask the uper 4 bit */
return *pModck_H;
}
/*******************************************************************************
*
* sysModck13Get - determines the value of MODCK[1-3] reset configuration value
*
* This routine determines the value of MODCK[1-3] reset configuration value
*
* NOTE: From 'Clock Configuration Modes' 8260 Manual
* User Dip Switch 6,7, and 8 must match Config Switch 6,7, 8
*
* RETURNS: MODCK[1-3] value
*
*/
UINT8 sysModck13Get
(
void
)
{
return sysUserSwitchGet() & 0x07; /* lower 3 bits are modck[1-3] */
}
/*******************************************************************************
*
* sysChipRev - determines revision of Chip installed
*
* This routine determines revision of Chip installed
*
* RETURNS: Chip revision
*
*/
UINT32 sysChipRev(void)
{
UINT32 ImmrRegAddr = vxImmrGet();
UINT32 ImmrValue;
ImmrRegAddr += 0x101A8;
ImmrValue = *(UINT32 *)ImmrRegAddr;
ImmrValue &= MASKNUM_MASK;
return (ImmrValue);
}
/*******************************************************************************
*
* sysCpmReset - issues a CPM reset command
*
* This routine issues a CPM reset command
*
* RETURNS: N/A
*
*/
void sysCpmReset
(
void
)
{
/* Get the location of the IMMR register. */
int immrVal = vxImmrGet();
/* Wait for any previous commands to finish */
while ( *M8260_CPCR( immrVal ) & M8260_CPCR_FLG )
{}
*M8260_CPCR( immrVal ) = M8260_CPCR_RESET | M8260_CPCR_FLG;
/* See if the command has been accepted. */
while ( *M8260_CPCR( immrVal ) & M8260_CPCR_FLG )
{}
return;
}
/*******************************************************************************
*
* sysUserSwitchGet - returns the value of the User Dip Switch
*
* This routine returns the value of the User Dip Switch
*
* NOTE: Reverse bits so S1 is MSB S8 is LSB
*
* RETURNS: Unsigned 8 bit value
*
*/
UINT8 sysUserSwitchGet
(
void
)
{
/* UINT8 swvalue;*/
UINT8 mod_char = 0;
return mod_char;
}
/*******************************************************************************
*
* chipInfoCheck - returns the value of the User Dip Switch
*
*
*/
STATUS chipInfoCheck(void)
{
UINT32 ImmrRegAddr = vxImmrGet();
UINT32 ImmrValue;
UINT32 temp32;
/*chip version*/
ImmrRegAddr += 0x101A8;
ImmrValue = *(UINT32 *)ImmrRegAddr;
printf("IMMR = 0x%x.\n",ImmrValue);
ImmrValue &= MASKNUM_MASK;
if(ImmrValue <= 0x24)
{
printf("MPC8260 is Hip3 chip.\n");
if(ImmrValue == 0x11) printf("Ver A.1.\n");
}
else
{
printf("MPC8260 is Hip4 chip.\n");
if(ImmrValue == 0x60) printf("Ver A.0.\n");
else if(ImmrValue == 0x62) printf("Ver B.1.\n");
}
/*BUS/CPU/CPM speed */
temp32 = sysInputFreqGet();
if(temp32 != ERROR) printf("Sys Input Freq = %dHz.\n",temp32);
temp32 = sysCoreFreqGet();
if(temp32 != ERROR) printf("Sys core Freq = %dHz.\n",temp32);
temp32 = sysCpmFreqGet();
if(temp32 != ERROR) printf("Sys cpm Freq = %dHz.\n",temp32);
return (OK);
}
/*******************************************************************************
*
* ledRunDisplay - display system operation OK
* author:yuecode.
*/
STATUS ledErrDisplay(void)
{
int immrVal = vxImmrGet() ;
*M8260_IOP_PAPAR( immrVal ) &= ~(PA7 | PA8); /*general i/o*/
*M8260_IOP_PADIR( immrVal ) |= ( PA8|PA7);
* M8260_IOP_PADAT(immrVal) &= ~PA8;
* M8260_IOP_PADAT(immrVal) |= PA7;
return OK;
}
/*******************************************************************************
*
* ledRunDisplay - display system operation OK
* author:yuecode.
*/
STATUS ledRunDisplay(void)
{
int immrVal = vxImmrGet() ;
*M8260_IOP_PAPAR( immrVal ) &= ~(PA7 | PA8); /*general i/o*/
*M8260_IOP_PADIR( immrVal ) |= ( PA7|PA8);
* M8260_IOP_PADAT(immrVal) &= ~PA7;
* M8260_IOP_PADAT(immrVal) |= PA8;
return OK;
}
/*******************************************************************************
*
* sysEnetAddrSet - sets the 6 byte ethernet address used by the ethernet device.
*
* This routine sets the 6 byte ethernet address used by the ethernet device.
*
* RETURNS: N/A
*/
void sysEnetAddrSet
(
int unit ,
unsigned char byte5,
unsigned char byte4,
unsigned char byte3,
unsigned char byte2,
unsigned char byte1,
unsigned char byte0
)
{
char *tmp;
glbEnetAddr[0] = byte5;
glbEnetAddr[1] = byte4;
glbEnetAddr[2] = byte3;
glbEnetAddr[3] = byte2;
glbEnetAddr[4] = byte1;
glbEnetAddr[5] = byte0;
tmp = glbEnetAddr;
}
/*******************************************************************************
*
* sysEnetAddrGet - gets the 6 byte ethernet address used by the ethernet device.
*
* This routine gets the 6 byte ethernet address used by the ethernet device.
*
* RETURNS: OK
*/
STATUS sysEnetAddrGet
(
int unit , /* not used */
UINT8 * addr /* Location address is returned in */
)
{
int n;
for ( n=0; n < MAC_ADRS_LEN ;n++) *(addr+n) = (char)glbEnetAddr[n];
return( OK ) ;
}
VOID Task_Delay (VOID)
{int i;
for(i=0;i<100000000;i++);
return;
}