www.pudn.com > Demo C.rar > IDpciDevices.c
/* IDpciDevices */
/* From: Darnold, Joel R */
/* Show information on PCI devices including vendor and parameters */
/* See PCIvenCodes.txt for additional information */
#include "vxWorks.h"
#include "stdio.h"
#include "sysLib.h"
#include "drv/pci/pciLocalBus.h"
#include "drv/pci/pciIomapLib.h"
#include "MyPCI.h"
STATUS pciDevConfig
(
int pciBusNo, /* PCI bus number */
int pciDevNo, /* PCI device number */
int pciFuncNo, /* PCI function number */
ULONG devIoBaseAdrs, /* device IO base address */
ULONG devMemBaseAdrs, /* device memory base address */
ULONG command /* command to issue */
);
struct ID_PCI_DEVICES
{
int PciVenId;
int PciDevId;
char VendorName[20];
char DeviceName[40];
};
/* externs */
IMPORT int pciLibInitDone;
IMPORT int pciLibInitStatus;
IMPORT int pciConfigMech;
STATUS IDpciDevices(int busNo)
{
int i=0;
int deviceNo;
int devices;
union {
int classCode;
char array[4];
} u;
struct pciHeaderDevice DeviceInfo;=20
struct ID_PCI_DEVICES IDpciDevices[NUM_IDS_DEFINED];
IDpciDevices[i].PciVenId = MOTOROLA_VEN_ID;
IDpciDevices[i].PciDevId = RAVEN_DEV_ID;
sprintf(IDpciDevices[i].VendorName,"Motorola");
sprintf(IDpciDevices[i].DeviceName,"Raven MPC/PCI Bridge");
i++;
IDpciDevices[i].PciVenId = SYMPHONY_VEN_ID;
IDpciDevices[i].PciDevId = W83C533_DEV_ID;
sprintf(IDpciDevices[i].VendorName,"Symphony");
sprintf(IDpciDevices[i].DeviceName,"W83C533 PCI/ISA Bridge");
i++;
IDpciDevices[i].PciVenId = TUNDRA_VEN_ID;
IDpciDevices[i].PciDevId = CA91C042_DEV_ID;
sprintf(IDpciDevices[i].VendorName,"Tundra");
sprintf(IDpciDevices[i].DeviceName,"CA91C042 Universe PCI/VME Bridge");
i++;
IDpciDevices[i].PciVenId = DEC_VEN_ID;
IDpciDevices[i].PciDevId = _21140_DEV_ID;
sprintf(IDpciDevices[i].VendorName,"Digital");
sprintf(IDpciDevices[i].DeviceName,"21140 Ethernet");
i++;
IDpciDevices[i].PciVenId = PLX_VEN_ID;
IDpciDevices[i].PciDevId = PCI9050_DEV_ID;
sprintf(IDpciDevices[i].VendorName,"PLX Technology");
sprintf(IDpciDevices[i].DeviceName,"PCI9050 PCI Interface (CLIB)");
i++;
IDpciDevices[i].PciVenId = PENTEK_VEN_ID;
IDpciDevices[i].PciDevId = _7110_DEV_ID;
sprintf(IDpciDevices[i].VendorName,"Pentek");
sprintf(IDpciDevices[i].DeviceName,"7110 C44 DSP PMC Module");
if (pciLibInitStatus != OK) /* sanity check */
return (ERROR);
printf ("Scanning function 0 of each PCI device on bus %d\n", busNo);
printf ("Using configuration mechanism %d\n", pciConfigMech);
printf ("bus dev func venID devID class description\n");
if (pciConfigMech == PCI_MECHANISM_1)
devices = 0x1f;
else
devices = 0x0f;
for (deviceNo=0; deviceNo < devices; deviceNo++)
{
pciConfigInWord (busNo, deviceNo, 0, PCI_CFG_VENDOR_ID, &DeviceInfo.vendorId);
pciConfigInWord (busNo, deviceNo, 0, PCI_CFG_DEVICE_ID, &DeviceInfo.deviceId);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_PROGRAMMING_IF,&u.array[3]);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_SUBCLASS, &u.array[2]);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_CLASS, &u.array[1]);
u.array[0] = 0;
/* There are two ways to find out an empty device.
* 1. check Master Abort bit after the access.
* 2. check whether the read value is 0xffff.
* Since I didn't see the Master Abort bit of the host/PCI bridge
* changing, I use the second method.
*/
if ((unsigned short)DeviceInfo.vendorId != 0xffff)
{
pciConfigInWord (busNo, deviceNo, 0, PCI_CFG_VENDOR_ID, &DeviceInfo.vendorId);
pciConfigInWord (busNo, deviceNo, 0, PCI_CFG_DEVICE_ID, &DeviceInfo.deviceId);
pciConfigInWord (busNo, deviceNo, 0, PCI_CFG_COMMAND, &DeviceInfo.command);
pciConfigInWord (busNo, deviceNo, 0, PCI_CFG_STATUS, &DeviceInfo.status);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_REVISION, &DeviceInfo.revisionId);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_PROGRAMMING_IF, &DeviceInfo.classCode);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_SUBCLASS, &DeviceInfo.progIf);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_CLASS, &DeviceInfo.cacheLine);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_CACHE_LINE_SIZE, &DeviceInfo.cacheLine);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_LATENCY_TIMER, &DeviceInfo.latency);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_HEADER_TYPE, &DeviceInfo.headerType);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_BIST, &DeviceInfo.bist);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_0, &DeviceInfo.base0);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_1, &DeviceInfo.base1);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_2, &DeviceInfo.base2);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_3, &DeviceInfo.base3);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_4, &DeviceInfo.base4);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_BASE_ADDRESS_5, &DeviceInfo.base5);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_CIS, &DeviceInfo.cis);
pciConfigInWord (busNo, deviceNo, 0, PCI_CFG_SUB_VENDER_ID, &DeviceInfo.subVendorId);
pciConfigInWord (busNo, deviceNo, 0, PCI_CFG_SUB_SYSTEM_ID, &DeviceInfo.subSystemId);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_EXPANSION_ROM, &DeviceInfo.romBase);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_RESERVED_0, &DeviceInfo.reserved0);
pciConfigInLong (busNo, deviceNo, 0, PCI_CFG_RESERVED_1, &DeviceInfo.reserved1);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_DEV_INT_LINE, &DeviceInfo.intLine);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_DEV_INT_PIN, &DeviceInfo.intPin);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_MIN_GRANT, &DeviceInfo.minGrant);
pciConfigInByte (busNo, deviceNo, 0, PCI_CFG_MAX_LATENCY, &DeviceInfo.maxLatency);
/* printf("Found device VendorID %x DeviceID %x\n",DeviceInfo.vendorId,DeviceInfo.deviceId); */
for(i=0; i\n",
busNo, deviceNo, 0,(unsigned short)DeviceInfo.vendorId,
(unsigned short)DeviceInfo.deviceId, u.classCode,
IDpciDevices[i].VendorName,IDpciDevices[i].DeviceName);
}
}
printf("vendorId 0x%.5x\n",(unsigned short)DeviceInfo.vendorId); /* vendor ID */
printf("deviceId 0x%.5x\n",(unsigned short)DeviceInfo.deviceId); /* device ID */
printf("command 0x%.5x\n",(unsigned short)DeviceInfo.command); /* command register */
printf("status 0x%.5x\n",(unsigned short)DeviceInfo.status); /* status register */
printf("revisionrId 0x%.3x\n",(unsigned char )DeviceInfo.revisionId); /* revision ID */
printf("classCode 0x%.3x\n",(unsigned char )DeviceInfo.classCode); /* class code */
printf("subClass 0x%.3x\n",(unsigned char )DeviceInfo.subClass); /* sub class code */
printf("progIf 0x%.3x\n",(unsigned char )DeviceInfo.progIf); /* programming interface */
printf("cacheLine 0x%.3x\n",(unsigned char )DeviceInfo.cacheLine); /* cache line */
printf("latency 0x%.3x\n",(unsigned char )DeviceInfo.latency); /* latency time */
printf("headerType 0x%.3x\n",(unsigned char )DeviceInfo.headerType); /* header type */
printf("bist 0x%.3x\n",(unsigned char )DeviceInfo.bist); /* BIST */
printf("base0 0x%.8x\n",(unsigned int )DeviceInfo.base0); /* base address 0 */
printf("base1 0x%.8x\n",(unsigned int )DeviceInfo.base1); /* base address 1 */
printf("base2 0x%.8x\n",(unsigned int )DeviceInfo.base2); /* base address 2 */
printf("base3 0x%.8x\n",(unsigned int )DeviceInfo.base3); /* base address 3 */
printf("base4 0x%.8x\n",(unsigned int )DeviceInfo.base4); /* base address 4 */
printf("base5 0x%.8x\n",(unsigned int )DeviceInfo.base5); /* base address 5 */
printf("cis 0x%.8x\n",(unsigned int )DeviceInfo.cis); /* cardBus CIS pointer */
printf("subVendorId 0x%.5x\n",(unsigned short)DeviceInfo.subVendorId); /* sub system vendor ID */
printf("subSystemId 0x%.5x\n",(unsigned short)DeviceInfo.subSystemId); /* sub system ID */
printf("romBase 0x%.8x\n",(unsigned int )DeviceInfo.romBase); /* expansion ROM base address */
printf("reserved0 0x%.8x\n",(unsigned int )DeviceInfo.reserved0); /* reserved */
printf("reserved1 0x%.8x\n",(unsigned int )DeviceInfo.reserved1); /* reserved */
printf("intLine 0x%.3x\n",(unsigned char )DeviceInfo.intLine); /* interrupt line */
printf("intPin 0x%.3x\n",(unsigned char )DeviceInfo.intPin); /* interrupt pin */
printf("minGrant 0x%.3x\n",(unsigned char )DeviceInfo.minGrant); /* min Grant */
printf("maxLatency 0x%.3x\n",(unsigned char )DeviceInfo.maxLatency); /* max Latency */
}
}
return (OK);
}
/* This routine writes data to PLX's local configuration */
/* registers. The data is written as little endian so we do */
/* a 32 bit endian swap before we write the data */
/* Remember.... eprom data requires no data swappage */
void PciDevWriteLocCfgReg(int PCIBase,int RegAddress, int Data)
{
int SwapData=0;
SwapData = (Data & 0xff) << 24;
SwapData |= (Data & 0xff00) << 8;
SwapData |= (Data & 0xff0000) >> 8;
SwapData |= (Data & 0xff000000) >> 24;
*(volatile int *)(PCIBase+RegAddress) = SwapData;
}
int PciDevReadLocCfgReg(int PCIBase, int RegAddress)
{
int SwapData=0,Data;
Data = *(volatile int *)(PCIBase+RegAddress);
SwapData = (Data & 0xff) << 24;
SwapData |= (Data & 0xff00) << 8;
SwapData |= (Data & 0xff0000) >> 8;
SwapData |= (Data & 0xff000000) >> 24;
return(SwapData);
}
/* The following are general purpose memory reading routines */
void Peek8(int Address)
{
char cData;
cData = *(volatile char *)Address;
printf("0x%x = 0x%x\n",Address, (0xff & (int)cData));
}
void Peek16(int Address)
{
short sData;
sData = *(volatile short *)Address;
printf("0x%x = 0x%x\n",Address, (0xffff & (int)sData));
}
void Peek32(int Address)
{
int iData;
iData = *(volatile int *)Address;
printf("0x%x = 0x%x\n",Address, iData);
}
void Poke8(int Address, int cData)
{
*(volatile char *)Address = (char)cData;
printf("0x%x = 0x%x\n",Address, (0xff & (int)cData));
}
void Poke16(int Address, int sData)
{
*(volatile short *)Address = (short)sData;
printf("0x%x = 0x%x\n",Address, (0xffff & (int)sData));
}
void Poke32(int Address, int iData)
{
*(volatile int *)Address = iData;
printf("0x%x = 0x%x\n",Address, iData);
}
void Init7110(void)
{
int pciBusNo,pciDevNo,pciFuncNo;
int iDummy,i;
short sDummy;
printf("\n\n");
printf("CPU_PCI_IO_ADRS 0x%x PCI_IO_ADRS 0x%x\n",CPU_PCI_IO_ADRS,PCI_IO_ADRS);
printf("CPU_PCI_MEM_ADRS 0x%x PCI_MEM_ADRS 0x%x\n\n",CPU_PCI_MEM_ADRS,PCI_MEM_ADRS);
/*
printf("CLIB_PCI_FIFO_ADRS 0x%x CLIB_PCI_ALTERA_ADRS 0x%x\n",CLIB_PCI_FIFO_ADRS,CLIB_PCI_ALTERA_ADRS);
printf("CLIB_CPU_FIFO_ADRS 0x%x CLIB_CPU_ALTERA_ADRS 0x%x\n\n",CLIB_CPU_FIFO_ADRS|CPU_PCI_MEM_ADRS,CLIB_CPU_ALTERA_ADRS|CPU_PCI_IO_ADRS);
*/
if((pciFindDevice(C44_PCI_DEVICE_ID&0xffff,
(C44_PCI_DEVICE_ID>>16)&0xffff,
0,&pciBusNo,&pciDevNo,&pciFuncNo) != ERROR))
{
/* Initialize PCI Configuration Registers enough to access Local Configuration Registers */
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_0, C44_PCI_MEM0_ADRS);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_0, &iDummy);
printf("PCI_CFG_BASE_ADDRESS_0 = 0x%x\n",iDummy);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_1, C44_PCI_IO0_ADRS);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_1, &iDummy);
printf("PCI_CFG_BASE_ADDRESS_1 = 0x%x\n",iDummy);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_2, 0);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_2, &iDummy);
printf("PCI_CFG_BASE_ADDRESS_2 = 0x%x\n",iDummy);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_3, 0);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_3, &iDummy);
printf("PCI_CFG_BASE_ADDRESS_3 = 0x%x\n",iDummy);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_4, 0);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_4, &iDummy);
printf("PCI_CFG_BASE_ADDRESS_4 = 0x%x\n",iDummy);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_5, 0);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_5, &iDummy);
printf("PCI_CFG_BASE_ADDRESS_5 = 0x%x\n",iDummy);
pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, ( PCI_CMD_MEM_ENABLE | PCI_CMD_IO_ENABLE));
pciConfigInWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_COMMAND, &sDummy );
printf("PCI_CFG_COMMAND = 0x%x\n",sDummy);
/* Now we can access Local Configuration Registers so begin to do so */
/* Register settings to enable basic communication to PLX9080 has been */
/* initialized from EEPROM at 7110 power on */
#ifdef SETUP_LOCAL_CONFIG_REGISTERS
PciDevWriteLocCfgReg(C44_PCI_MEM0_ADRS, CNTRL, 0x00ff7580);/*0x00ff7580*//*0x00ff3580*//*0x00fd3580*/ /* Control */
PciDevWriteLocCfgReg(C44_PCI_MEM0_ADRS, LAS0RR, 0x0ffffff0); /* Fifo mapping */
PciDevWriteLocCfgReg(C44_PCI_MEM0_ADRS, LAS0BA, 0x000003c1); /* A0 & A1 of Local bus aren't used */
PciDevWriteLocCfgReg(C44_PCI_MEM0_ADRS, LAS0BRD,0x0180003f); /*0x01800022*//*0x0180003f*//*0x0180003a*//*0x0180001a*//* Fifo A0 = Local A2 */
PciDevWriteLocCfgReg(C44_PCI_MEM0_ADRS, CS0BASE, 0x000003c5); /* Fifo A1 = Local A3 */
/* Shift Address bits accordingly */
PciDevWriteLocCfgReg(C44_PCI_MEM0_ADRS, LAS1RR, 0x0fffffe1); /* Altera mapping */
PciDevWriteLocCfgReg(C44_PCI_MEM0_ADRS, LAS1BA, 0x00000141); /* A0 & A1 of Local bus aren't used */
PciDevWriteLocCfgReg(C44_PCI_MEM0_ADRS, LAS1BRD, 0x014060c2); /* Altera A0 = Local A2 */
PciDevWriteLocCfgReg(C44_PCI_MEM0_ADRS, CS1BASE, 0x00000000); /* Altera A1 = Local A3 */
/* Shift Address bits accordingly */
/* Now we can enable these memory maps in the PCI Configuration Registers */
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_2, C44_PCI_FIFO_ADRS);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_2, &iDummy);
printf("PCI_CFG_BASE_ADDRESS_2 = 0x%x\n",iDummy);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_3, CLIB_PCI_ALTERA_ADRS);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_3, &iDummy);
printf("PCI_CFG_BASE_ADDRESS_3 = 0x%x\n",iDummy);
#endif
}
else
{
printf("Error initializing Pentek 7110\n");
}
printf(" 7110 setup: pciBusNo = %d\n",pciBusNo);
printf(" pciDevNo = %d\n",pciDevNo);
printf(" pciFuncNo = %d\n",pciFuncNo);
printf(" C44_PCI_IO0_ADRS 0x%x\n",C44_PCI_IO0_ADRS);
printf(" C44_PCI_MEM0_ADRS 0x%x\n",C44_PCI_MEM0_ADRS);
printf("\nLocal configuration registers\n");
for(i=0; i<12; i++)
{
iDummy = PciDevReadLocCfgReg(C44_PCI_MEM0_ADRS,(i*4));
printf("0x%x = 0x%x\n",(i*4), iDummy);
} =09
for(i=16; i<20; i++)
{
iDummy = PciDevReadLocCfgReg(C44_PCI_MEM0_ADRS,(i*4));
printf("0x%x = 0x%x\n",(i*4), iDummy);
} =09
for(i=24; i<29; i++)
{
iDummy = PciDevReadLocCfgReg(C44_PCI_MEM0_ADRS,(i*4));
printf("0x%x = 0x%x\n",(i*4), iDummy);
} =09
}
void PCIReadBack7110(void)
{
int pciBusNo,pciDevNo,pciFuncNo;
int Bar0,Bar1,Bar2,Bar3,Bar4,Bar5;
if((pciFindDevice(C44_PCI_DEVICE_ID&0xffff,
(C44_PCI_DEVICE_ID>>16)&0xffff,
0,&pciBusNo,&pciDevNo,&pciFuncNo) != ERROR))
{
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_0, 0xffffffff);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_1, 0xffffffff);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_2, 0xffffffff);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_3, 0xffffffff);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_4, 0xffffffff);
pciConfigOutLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_5, 0xffffffff);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_0, &Bar0);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_1, &Bar1);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_2, &Bar2);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_3, &Bar3);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_4, &Bar4);
pciConfigInLong (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_BASE_ADDRESS_5, &Bar5);
printf(" 7110 PCI Readback Base Address Registers\n");
printf(" PCI_CFG_BASE_ADDRESS_0 = 0x%x\n",Bar0);
printf(" PCI_CFG_BASE_ADDRESS_1 = 0x%x\n",Bar1);
printf(" PCI_CFG_BASE_ADDRESS_2 = 0x%x\n",Bar2);
printf(" PCI_CFG_BASE_ADDRESS_3 = 0x%x\n",Bar3);
printf(" PCI_CFG_BASE_ADDRESS_4 = 0x%x\n",Bar4);
}
else
{
printf("Error initializing CLIB\n");
}
}