www.pudn.com > ScriptsSample.zip > S8XX.H
/*--------------------------------------------------*/
/* */
/* Module S8XX.H */
/* */
/* Declarations for Symbios Logic 8xx family SCSI */
/* I/O controllers. */
/* Register and other declarations. */
/* */
/* Adapted from Symbios Logic */
/* Software Development Kit */
/* */
/* Project: A Programmer's Guide to SCSI */
/* Copyright (C) 1997, Brian Sawert. */
/* All rights reserved. */
/* */
/*--------------------------------------------------*/
#ifndef _S8XX_H
#define _S8XX_H
/*---------- constant definitions ----------*/
/*---------- Symbios specific constants ----------*/
// Symbios Logic vendor ID
#define PCI_SYM_VENDOR_ID 0x1000
// SYM53C825 device ID
#define C825_DEVICE_ID 0x0003
// SYM53C825 device version ID
#define C825_VERSION_ID 0x00
// SYM53C825 I/O base config offset
#define C8XX_CONFIG_REG_IOB 0x10
// SYM53C825 memory base config offset
#define C8XX_CONFIG_REG_MEMB 0x14
// SYM53C825 SCRIPTS RAM base config offset
#define C8XX_CONFIG_REG_RAMB 0x18
// default clock conversion factor
#define DEF_CLOCK 0x03
// default selection timeout
#define DEF_SELECT_TO 0x0C
/*---------- 53C8XX register offsets ----------*/
#define SCNTL0 0x00
#define SCNTL1 0x01
#define SCNTL2 0x02
#define SCNTL3 0x03
#define SCID 0x04
#define SXFER 0x05
#define SDID 0x06
#define GPREG 0x07
#define SFBR 0x08
#define SOCL 0x09
#define SSID 0x0A
#define SBCL 0x0B
#define DSTAT 0x0C
#define SSTAT0 0x0D
#define SSTAT1 0x0E
#define SSTAT2 0x0F
#define DSA 0x10
#define ISTAT 0x14
#define CTEST0 0x18
#define CTEST1 0x19
#define CTEST2 0x1A
#define CTEST3 0x1B
#define TEMP 0x1C
#define DFIFO 0x20
#define CTEST4 0x21
#define CTEST5 0x22
#define CTEST6 0x23
#define DBC 0x24
#define DCMD 0x27
#define DNAD 0x28
#define DSP 0x2C
#define DSPS 0x30
#define SCRATCHA 0x34
#define DMODE 0x38
#define DIEN 0x39
#define SBR 0x3A
#define DCNTL 0x3B
#define ADDER 0x3C
#define SIEN0 0x40
#define SIEN1 0x41
#define SIST0 0x42
#define SIST1 0x43
#define SLPAR 0x44
#define SWIDE 0X45
#define MACNTL 0x46
#define GPCNTL 0x47
#define STIME0 0x48
#define STIME1 0x49
#define RESPID0 0x4A
#define RESPID1 0x4B
#define STEST0 0x4C
#define STEST1 0x4D
#define STEST2 0x4E
#define STEST3 0x4F
#define SIDL 0x50
#define SODL 0x54
#define SODL1 0x55
#define SBDL 0x58
#define SCRATCHB 0x5C
#define SCRATCHC 0x60
#define SCRATCHD 0x64
#define SCRATCHE 0x68
#define SCRATCHF 0x6C
#define SCRATCHG 0x70
#define SCRATCHH 0x74
#define SCRATCHI 0x78
#define SCRATCHJ 0x7C
/*---------- 53C8XX interrupt bits ----------*/
//---------- ISTAT register bits
// DMA interrupt pending
#define C8XX_INT_DIP 0x01
// SCSI interrupt pending
#define C8XX_INT_SIP 0x02
//---------- DSTAT register bits
// master parity error
#define C8XX_INT_MDPE 0x40
// bus fault
#define C8XX_INT_BF 0x20
// SCRIPTS aborted
#define C8XX_INT_ABRT 0x10
// SCRIPTS step interrupt
#define C8XX_INT_SSI 0x08
// SCRIPTS interrupt instruction
#define C8XX_INT_SIR 0x04
// SCRIPTS illegal instruction detected
#define C8XX_INT_IID 0x01
//---------- SIST register bits
// phase mismatch
#define C8XX_INT_MA 0x0080
// function complete
#define C8XX_INT_CMP 0x0040
// selected
#define C8XX_INT_SEL 0x0020
// reselected
#define C8XX_INT_RSL 0x0010
// SCSI gross error
#define C8XX_INT_SGE 0x0008
// unexpected disconnect
#define C8XX_INT_UDC 0x0004
// SCSI reset received
#define C8XX_INT_RST 0x0002
// SCSI parity error
#define C8XX_INT_PAR 0x0001
// SCSI selection timeout
#define C8XX_INT_STO 0x0400
// general purpose timer int
#define C8XX_INT_GEN 0x0200
// handshake to handshake int
#define C8XX_INT_HTH 0x0100
/*---------- bit encoded chip features ----------*/
#define C8XX_WIDE_SCSI 0x00000001L
#define C8XX_ROM_IF 0x00000002L
#define C8XX_DIFF_SCSI 0x00000004L
#define C8XX_BRST_OP 0x00000008L
#define C8XX_PREFETCH 0x00000010L
#define C8XX_SRAM 0x00000020L
#define C8XX_CACHE 0x00000040L
#define C8XX_SSAID 0x00000080L
#define C8XX_EX_TIMER 0x00000100L
#define C8XX_EX_SLPAR 0x00000200L
#define C8XX_EN_RMOVE 0x00000400L
#define C8XX_IRQ_DIS 0x00000800L
#define C8XX_LD_STR 0x00001000L
#define C8XX_FAST20 0x00002000L
#define C8XX_32SCRATCH 0x00004000L
#define C8XX_CLK_DBLR 0x00008000L
#define C8XX_FAST40 0x00010000L
#define C8XX_64BITPCI 0x00020000L
/*---------- burst size codes ----------*/
#define C8XX_BURST_2 0
#define C8XX_BURST_4 1
#define C8XX_BURST_8 2
#define C8XX_BURST_16 3
#define C8XX_BURST_32 4
#define C8XX_BURST_64 5
#define C8XX_BURST_128 6
// C8XX device information
typedef struct {
BYTE scsi_id;
WORD dev_id;
BYTE rev_id;
WORD fifo_size_a;
WORD fifo_size_b;
BYTE max_burst_a;
BYTE max_burst_b;
BYTE max_offset;
DWORD features;
} c8xx_device;
// 53C825 specific values
#define C8XX_53C825_FIFO_A 64
#define C8XX_53C825_FIFO_B 0
#define C8XX_53C825_BRST_A C8XX_BURST_16
#define C8XX_53C825_BRST_B 0
#define C8XX_53C825_OFFSET 8
#define C8XX_53C825_FEAT \
(C8XX_WIDE_SCSI | C8XX_ROM_IF | C8XX_DIFF_SCSI | C8XX_BRST_OP)
/*---------- macro definitions ----------*/
/*---------- 53C8XX function declarations ----------*/
// initialize 53C8XX chip
extern WORD init_8xx(pci_device *ppcidev,
c8xx_device *pc8xxdev);
#endif